The present invention relates to a semiconductor device, and more particularly, to a technology for screening the connectivity of a through silicon via (TSV) at a wafer level.
Recently, in order to enhance integration of semiconductor devices, there has been developed a three-dimensional (3D) semiconductor device where a plurality of chips are stacked and packaged in a single package.
In the 3D semiconductor device, two or more chips are vertically stacked so that substantially increased integration may be obtained in the same space as that of a typical semiconductor device.
Specifically, a through silicon via (TSV) method has been used in which a TSV penetrates through a plurality of stacked chips to electrically couple the chips to each other.
Since a semiconductor device using a TSV is configured to connect chips by allowing the TSV to vertically penetrate the chips, the semiconductor device using the TSV can reduce a package area more effectively than a conventional semiconductor device configured to couple chips through a border line using a wire.
FIG. 1 illustrates a cross-sectional view of a conventional semiconductor device.
If a TSV is used, a plurality of chips each having the same structure are stacked to implement a single semiconductor device.
The semiconductor device generally includes one master chip 10 to control an operation of the semiconductor device and a plurality of slave chips 20 each configured to perform an operation for storing data.
The master chip 10 includes a pad and a logic circuit located in a peripheral region. The master chip 10 may further include a memory core. The slave chip 20 includes a memory core, a logic circuit for repair, and a logic circuit for TSV coupling.
The slave chip 20 coupled to a second circuit 24 is located over the master chip 10 coupled to a first circuit 14.
In the master chip 10, a first metal layer 11 is formed over a first TSV TSV1, and a metal contact 12 is formed over the first metal layer 11.
A second metal layer 13 coupled to the first circuit 14 is formed over the metal contact 12.
In the slave chip 20, a first metal layer 21 is formed over a second TSV TSV2, and a metal contact 22 is formed over the first metal layer 21.
A second metal layer 23 coupled to the second circuit 24 is formed over the metal contact 22.
In the conventional semiconductor device having the above-described structure, the chips are formed at a wafer level, and a stacking and packaging process is performed after a dicing process is performed, thereby forming a package. After that, a process of verifying TSV connectivity between the chips is performed.
Since the verifying process is performed after the packaging process, it is impossible to screen for defects in TSV connectivity generated at a wafer level.
FIG. 2 illustrates a cross-sectional view for showing a problem that occurs in a conventional TSV structure as shown in FIG. 1.
In the TSV structure for a multi-chip package, a copper (Cu) material, which fills in a TSV, is expanded by a subsequent heat treatment process.
As a result, a crack is generated in the TSV, a defect of disconnecting the TSV from a metal layer formed over the TSV, e.g., the first metal layer MT1 or the second layer MT2, may occur.
In this case, an operational failure of the TSV is verified only at a package level, thus inducing unnecessary costs associated with packaging chips having defects in their connectivity.
That is, the TSV structure is a necessary technique factor for DRAM operations of high capacity with a high speed.
Like TSV, a mid-level structure which does not require large costs without a large change of an inline process can check the connectivity of chips after the stacking process.
That is, when defects in the TSV connectivity are caused at wafer level, it is impossible to screen for defects at a wafer level, resulting in inducing unnecessary costs associated with packaging defective chips.